1. Field of the Invention
The present invention relates to a signal transmission technology for enabling high-speed signal transmission between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or cabinets, and more particularly to a data receiving circuit for performing high-speed signal transmission.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories), and other semiconductor devices such as processors and switching LSIs.
The improvements in the performance of semiconductor memory devices, processors, etc. have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased. Specifically, the speed gap between a semiconductor memory device such as a SRAM or DRAM and a processor, for example, has been widening, and in recent years, this speed gap has become a bottleneck in boosting a computer's overall performance.
Furthermore, the need for an improvement in signal transmission speed is increasing not only for signal transmission between cabinets or boards (printed wiring boards), such as between a server and a main storage device or between servers connected via a network, but also for signal transmission between chips or between devices or circuit blocks within a single chip because of increasing integration and increasing size of semiconductor chips, decreasing supply voltage levels (decreasing signal amplitude levels), etc.
More specifically, there is a need to increase the signal transmission speed per pin in order to address the increase in the amount of data transmission between LSIs or between boards or cabinets. This is also necessary to avoid an increase in package cost, etc. due to an increased pin count. As a result, inter-LSI signal transmission speeds exceeding 2.5 Gbps have been achieved in recent years, and it is now desired to achieve extremely high speeds (high-speed signal transmission) reaching or even exceeding 10 Gbps.
Generally, when constructing a data receiving circuit operating at high speed, it is practiced to provide a demultiplexer (DEMUX) at a position as close as possible to an input data line (data input terminal) within the receiving circuit in order to convert the input data to signals of slower frequency components at the position close to the data input terminal. The DEMUX used in the data receiving circuit has also the function of a sampling circuit, and samples high-speed input data for output as slow-speed data.
However, when the speed of signal transmission between circuit blocks or chips or between cabinets or boards is increased, signal attenuation through signal transmission lines increases and, as a result, the amplitude of the signal received at the data receiving circuit decreases. Furthermore, at the data transmitting circuit also, it becomes difficult to output a large amplitude signal, resulting in a further decrease in the amplitude of the received signal. It is therefore needed to provide a data receiving circuit that has high sensitivity, is capable of operating at high speed, and yet can correctly receive data despite the attenuation of high-frequency signal components.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.